Study on bump arrangement to accelerate the underfill flow in flip-chip packaging

Shih Wei Lin, Wen Bin Young

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


Flip-chip packaging is an integrated circuit packaging technique that uses solder bumps to connect chip with substrate. The underfill process uses epoxy encapsulant to solve this problem and improves the reliability of flip-chip packaging. The encapsulant is filled into the gap between the chip and substrate by the capillary force so that the thermal stresses may disperse into the underfill materials to avoid crack generation. The filling time in the underfill process strongly depends on the arrangement of the solder bumps. The edge effect can enhance the filling speed during the underfill encapsulation if the void formation can be avoided. With distributed bump pitch design, the filling time of the underfill can be reduced. There exists an optimal selection of the pitch variation during the use of distributed bump pitch. Another method of using a center bump-free channel can also increase the filling efficiency. The optimization method is used to determine the size of the channel that is found to increase the filling speed dramatically in the case of underfill of the chip with a fine bump pitch.

Original languageEnglish
Article number6363586
Pages (from-to)40-45
Number of pages6
JournalIEEE Transactions on Components, Packaging and Manufacturing Technology
Issue number1
Publication statusPublished - 2013

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


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