Abstract
The configurations and adjusting method of a successive approximation analog-to-digital converter (SAR ADC) are provided. The provided SAR ADC includes at least one capacitor with a first and a second terminals, and a plurality of bits, each of which is connected to the at least one capacitor, wherein the first terminal receives an input signal, and the second terminal selectively receives one of a first and a second reference voltages, and a first comparator receiving an adjustable third reference voltage and a first voltage value generated by the input signal, wherein a connection of the second terminal of each the capacitor of the capacitor array is switched when the first voltage value is larger than the third reference voltage.
| Translated title of the contribution | 具輔助預測電路之逐漸趨近式類比數位轉換器及其方法 |
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| Original language | English |
| Patent number | 8416116 |
| Publication status | Published - 2012 Jun 21 |