Switch level test generation (SLTG) is potentially more powerful than conventional gate level test generation (GLTG) or CMOS circuits. Over the last decade much research has been carried out on SLTG. However to date no widely accepted SLTG system exists. The objectives of this work are to analyze the various problems associated with SLTG, to identify a feasible way to deal with these problems, and to develop an efficient and useful SLTG system for combinational circuits. The basic idea is to make use of as many GLTG concepts as possible without modeling a CMOS circuit at the gate level. Based on the analysis of CMOS circuits and faults, a SLTG system called SWiTEST has been developed. This system can deal with bridging, transistor stuck-open, transistor stuck-on and stuck-at faults. It employs both logic and current (IDDQ testing) monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework of this system is PODEM-based. To be applicable to switch level circuits, the basic PODEM algorithm has been enhanced to deal with concepts such as multiple objective selection, search-based backtracing and incremental event-driven logic implication. Experimental results indicate that SWiTEST is quite efficient in both CPU time and memory usage.
|Number of pages||13|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - 1994 May|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering