We present a novel design methodology for synthesizing multiple configurations (or modes) into a single programmable system. Many DSP and multimedia applications require reconfigurability of a system along with efficiency in terms of power performance and area. FPGAs provide a reconfigurable platform, however, they are slower in speed with significantly higher power consumption than achievable by a customized ASIC. In this work, we have developed techniques to realize an efficient reconfigurable system for a set of user-specified configurations. A data flow graph transformation method coupled with efficient scheduling and allocation are used to automatically synthesize the system from its behavioral level specifications. Experimental results on several applications demonstrate that we can achieve about 60× power reduction on average with about 4× improvement in performance over corresponding FPGA implementations.
|Number of pages||6|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|Publication status||Published - 2003 Dec 1|
|Event||Design, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany|
Duration: 2003 Mar 3 → 2003 Mar 7
All Science Journal Classification (ASJC) codes