TY - GEN
T1 - System-level development and verification framework for high-performance system accelerator
AU - Wang, Chen Chieh
AU - Wong, Ro Pun
AU - Lin, Jing Wun
AU - Chen, Chung-Ho
PY - 2009/12/1
Y1 - 2009/12/1
N2 - In this paper, we propose a framework to develop high-performance system accelerator at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication support that enables full system simulation. We have also developed a network virtual interface for our system to co-work with the real world network environment. Finally, the MD5 algorithm offload and the network offload engine are used as examples to demonstrate the proposed framework system for full system simulation.
AB - In this paper, we propose a framework to develop high-performance system accelerator at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication support that enables full system simulation. We have also developed a network virtual interface for our system to co-work with the real world network environment. Finally, the MD5 algorithm offload and the network offload engine are used as examples to demonstrate the proposed framework system for full system simulation.
UR - http://www.scopus.com/inward/record.url?scp=77950653439&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77950653439&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2009.5158169
DO - 10.1109/VDAT.2009.5158169
M3 - Conference contribution
AN - SCOPUS:77950653439
SN - 9781424427826
T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
SP - 359
EP - 362
BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Y2 - 28 April 2009 through 30 April 2009
ER -