TY - GEN
T1 - System-level test coverage prediction by structural stress test data mining
AU - Lin, Bing Yang
AU - Wu, Cheng Wen
AU - Chen, Harry H.
PY - 2015/5/28
Y1 - 2015/5/28
N2 - To achieve high quality of silicon ICs, system-level test (SLT) can be performed after regular final test. This is important for chips manufactured in advanced technologies, as systematic failures are getting harder to detect by conventional structural tests. However, due to long test time and extra human efforts, the cost for SLT is high. A possible way to replace SLT without quality loss is to identify SLT failure suspects with stress tests. In this work, we apply 60,000 structural stress test patterns to the CPU blocks of a real SOC product, using 20 stressed voltage-frequency corners. We try to identify the correlation between the stress test data and SLT-pass/fail results of the CPU blocks. By the proposed differential feature-based methodology, 32 outliers are identified, which are assumed to be CPU-fail chips. Because of the lack of exact CPU-fail chip IDs for verification, the identified chip IDs are compared with the IDs identified from previous works, which use the same data but different machine-learning features and method for the same purpose. After comparison, 30 out of a total of 33 CPU-fail suspects matched. Although this does not immediately imply that the SLT can be replaced by the structural stress tests, it shows more evidence that test data mining can be further explored for test time reduction and/or quality improvement.
AB - To achieve high quality of silicon ICs, system-level test (SLT) can be performed after regular final test. This is important for chips manufactured in advanced technologies, as systematic failures are getting harder to detect by conventional structural tests. However, due to long test time and extra human efforts, the cost for SLT is high. A possible way to replace SLT without quality loss is to identify SLT failure suspects with stress tests. In this work, we apply 60,000 structural stress test patterns to the CPU blocks of a real SOC product, using 20 stressed voltage-frequency corners. We try to identify the correlation between the stress test data and SLT-pass/fail results of the CPU blocks. By the proposed differential feature-based methodology, 32 outliers are identified, which are assumed to be CPU-fail chips. Because of the lack of exact CPU-fail chip IDs for verification, the identified chip IDs are compared with the IDs identified from previous works, which use the same data but different machine-learning features and method for the same purpose. After comparison, 30 out of a total of 33 CPU-fail suspects matched. Although this does not immediately imply that the SLT can be replaced by the structural stress tests, it shows more evidence that test data mining can be further explored for test time reduction and/or quality improvement.
UR - http://www.scopus.com/inward/record.url?scp=84936972499&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84936972499&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2015.7114508
DO - 10.1109/VLSI-DAT.2015.7114508
M3 - Conference contribution
AN - SCOPUS:84936972499
T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Y2 - 27 April 2015 through 29 April 2015
ER -