Systolic VLSI realization of a novel iterative division algorithm over GF(2m): A high-speed, low-complexity design

C. H. Wu, C. M. Wu, Ming-Der Shieh, Y. T. Hwang

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

We present a parallel-in parallel-out systolic division circuit over GF(2m) based on the novel extended Stein's algorithm that provides guaranteed convergence in 2m-1 iterations. The area-time (AT) complexity of our design is O(m2) and the achievable maximum clock rate is 1 GHz based on the 0.6μm technology. Compared to the best systolic design known to date based on the extended Euclid's algorithm, the proposed circuit exhibits significant area and speed advantages.

Original languageEnglish
JournalMaterials Research Society Symposium - Proceedings
Volume626
Publication statusPublished - 2001 Jan 1
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

Fingerprint

very large scale integration
division
high speed
Networks (circuits)
clocks
iteration
Clocks

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

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title = "Systolic VLSI realization of a novel iterative division algorithm over GF(2m): A high-speed, low-complexity design",
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year = "2001",
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journal = "Materials Research Society Symposium - Proceedings",
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Systolic VLSI realization of a novel iterative division algorithm over GF(2m) : A high-speed, low-complexity design. / Wu, C. H.; Wu, C. M.; Shieh, Ming-Der; Hwang, Y. T.

In: Materials Research Society Symposium - Proceedings, Vol. 626, 01.01.2001.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Systolic VLSI realization of a novel iterative division algorithm over GF(2m)

T2 - A high-speed, low-complexity design

AU - Wu, C. H.

AU - Wu, C. M.

AU - Shieh, Ming-Der

AU - Hwang, Y. T.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - We present a parallel-in parallel-out systolic division circuit over GF(2m) based on the novel extended Stein's algorithm that provides guaranteed convergence in 2m-1 iterations. The area-time (AT) complexity of our design is O(m2) and the achievable maximum clock rate is 1 GHz based on the 0.6μm technology. Compared to the best systolic design known to date based on the extended Euclid's algorithm, the proposed circuit exhibits significant area and speed advantages.

AB - We present a parallel-in parallel-out systolic division circuit over GF(2m) based on the novel extended Stein's algorithm that provides guaranteed convergence in 2m-1 iterations. The area-time (AT) complexity of our design is O(m2) and the achievable maximum clock rate is 1 GHz based on the 0.6μm technology. Compared to the best systolic design known to date based on the extended Euclid's algorithm, the proposed circuit exhibits significant area and speed advantages.

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M3 - Conference article

AN - SCOPUS:0035030882

VL - 626

JO - Materials Research Society Symposium - Proceedings

JF - Materials Research Society Symposium - Proceedings

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