Systolic VLSI realization of a novel iterative division algorithm over GF(2): A high-speed, low-complexity design

Chien Hsing Wu, Chien Ming Wu, Ming-Der Shieh, Yin Tsung Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

We present a parallel-in parallel-out systolic division circuit over GF(2/sup m/) based on the novel extended Stein's algorithm that provides guaranteed convergence in 2/sup m/-1 iterations. The area-time (AT) complexity of our design is O(m/sup 2/) and the achievable maximum clock rate is 1 GHz based on the 0.6 /spl mu/m technology. Compared to the best systolic design known to date based on the extended Euclid's algorithm the proposed circuit exhibits significant area and speed advantages.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages33-36
Number of pages4
Volume4
DOIs
Publication statusPublished - 2001
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01-05-0601-05-09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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