Test algorithm and bist design for mram write disturbance fault

Ching Yi Chen, Wan Yu Lo, Chin Lung Su, Cheng Wen Wu

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

The write disturbance fault (WDF) model is a fault model specific to MRAM which implies that the data stored in the MRAM cells is changed due to excessive magnetic field during a Write operation. March tests have high coverage for conventional RAM faults. However, they do not detect all WDFs. To improve the quality and yield of MRAM, we propose a new test algorithm to detect WDF for MRAM in this paper, and further apply the proposed algorithm to test MRAM chips. Fault coverage of proposed test algorithm is higher than that of traditional March test algorithms. Also, we develop a built-in self-test (BIST) circuit that supports the proposed test method. A 128Kb MRAM prototype chip with proposed BIST circuit has been designed and fabricated using a special 0.15 um CMOS technology.

Original languageEnglish
Pages (from-to)63-70
Number of pages8
JournalInternational Journal of Electrical Engineering
Volume15
Issue number2
Publication statusPublished - 2008 Apr 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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