Test and diagnosis of word-oriented multiport memories

Chih Wea Wang, Kuo Liang Cheng, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)


Conventionally, the test of multiport memories is considered difficult because of the complex behavior of the faulty memories and the large number of inter-port faults. This paper presents an efficient approach for testing and diagnosing multiport RAMs. Our approach takes advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides higher observability and controllability that effectively reduces the test time. Our key idea is that a sequence of March operations for any memory cell can be folded and executed within a single access cycle. We have also developed an efficient test algorithm for port-specific faults as well as traditional cell faults. The port-specific faults include the stuck-open, address decoder, and inter-port faults, for both bit-oriented and word-oriented RAMs. Experimental results for our folding scheme show that the test time reduction is about 28% for a commercial 8 KB embedded SRAM. An efficient diagnostic algorithm is also proposed for the port-specific faults and traditional cell faults.

Original languageEnglish
Title of host publicationProceedings - 21st IEEE VLSI Test Symposium, VTS 2003
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)0769519245
Publication statusPublished - 2003 Jan 1
Event21st IEEE VLSI Test Symposium, VTS 2003 - Napa Valley, United States
Duration: 2003 Apr 272003 May 1

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference21st IEEE VLSI Test Symposium, VTS 2003
Country/TerritoryUnited States
CityNapa Valley

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering


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