Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults

Cheng Hung Wu, Saint James Lee, Kuen Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A dynamic bridging fault (DBF) induces a transition delay on a circuit node and hence has fault effects similar to a transition delay fault (TDF). However the causes of these two types of faults are quite different: a DBF is due to the bridging effects between two circuit nodes, while a TDF is due to a node itself or the logic connected to the node. In this paper we present an efficient test and diagnosis pattern generation procedure to detect DBFs and TDFs as well as to distinguish them such that the exact sources of defects can be identified during the yield ramping process. We first analyze the dominance relation between a DBF and its corresponding TDF. A new circuit model called the inverse DBF (IDBF) model is then employed which can transform the problem of distinguishing a pair of a DBF and a TDF into the problem of detecting the inverse DBF. The pattern generation process can then be done by using an ATPG tool for dynamic bridging faults. A complete procedure to generate both test and diagnosis patterns to detect all testable TDFs and DBFs as well as to distinguish them is then presented. In this flow all TDFs, DBFs, and all fault pairs between the two types of faults can be modeled in a single circuit and dealt with in a few ATPG runs. Thus the pattern generation process is quite efficient and very compact pattern sets can be obtained by utilizing the test pattern compaction feature of the ATPG tool. Experimental results on ISCAS89 benchmarks show that our procedure can detect all detectable TDFs and DBFs and 99.94% of fault pairs between DBFs and TDFs can either be distinguished or identified as equivalent-fault pairs.

Original languageEnglish
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages755-760
Number of pages6
ISBN (Electronic)9781467395694
DOIs
Publication statusPublished - 2016 Mar 7
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: 2016 Jan 252016 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period16-01-2516-01-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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