TY - GEN
T1 - Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults
AU - Wu, Cheng Hung
AU - Lee, Saint James
AU - Lee, Kuen Jong
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/3/7
Y1 - 2016/3/7
N2 - A dynamic bridging fault (DBF) induces a transition delay on a circuit node and hence has fault effects similar to a transition delay fault (TDF). However the causes of these two types of faults are quite different: a DBF is due to the bridging effects between two circuit nodes, while a TDF is due to a node itself or the logic connected to the node. In this paper we present an efficient test and diagnosis pattern generation procedure to detect DBFs and TDFs as well as to distinguish them such that the exact sources of defects can be identified during the yield ramping process. We first analyze the dominance relation between a DBF and its corresponding TDF. A new circuit model called the inverse DBF (IDBF) model is then employed which can transform the problem of distinguishing a pair of a DBF and a TDF into the problem of detecting the inverse DBF. The pattern generation process can then be done by using an ATPG tool for dynamic bridging faults. A complete procedure to generate both test and diagnosis patterns to detect all testable TDFs and DBFs as well as to distinguish them is then presented. In this flow all TDFs, DBFs, and all fault pairs between the two types of faults can be modeled in a single circuit and dealt with in a few ATPG runs. Thus the pattern generation process is quite efficient and very compact pattern sets can be obtained by utilizing the test pattern compaction feature of the ATPG tool. Experimental results on ISCAS89 benchmarks show that our procedure can detect all detectable TDFs and DBFs and 99.94% of fault pairs between DBFs and TDFs can either be distinguished or identified as equivalent-fault pairs.
AB - A dynamic bridging fault (DBF) induces a transition delay on a circuit node and hence has fault effects similar to a transition delay fault (TDF). However the causes of these two types of faults are quite different: a DBF is due to the bridging effects between two circuit nodes, while a TDF is due to a node itself or the logic connected to the node. In this paper we present an efficient test and diagnosis pattern generation procedure to detect DBFs and TDFs as well as to distinguish them such that the exact sources of defects can be identified during the yield ramping process. We first analyze the dominance relation between a DBF and its corresponding TDF. A new circuit model called the inverse DBF (IDBF) model is then employed which can transform the problem of distinguishing a pair of a DBF and a TDF into the problem of detecting the inverse DBF. The pattern generation process can then be done by using an ATPG tool for dynamic bridging faults. A complete procedure to generate both test and diagnosis patterns to detect all testable TDFs and DBFs as well as to distinguish them is then presented. In this flow all TDFs, DBFs, and all fault pairs between the two types of faults can be modeled in a single circuit and dealt with in a few ATPG runs. Thus the pattern generation process is quite efficient and very compact pattern sets can be obtained by utilizing the test pattern compaction feature of the ATPG tool. Experimental results on ISCAS89 benchmarks show that our procedure can detect all detectable TDFs and DBFs and 99.94% of fault pairs between DBFs and TDFs can either be distinguished or identified as equivalent-fault pairs.
UR - http://www.scopus.com/inward/record.url?scp=84996757793&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84996757793&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2016.7428102
DO - 10.1109/ASPDAC.2016.7428102
M3 - Conference contribution
AN - SCOPUS:84996757793
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 755
EP - 760
BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Y2 - 25 January 2016 through 28 January 2016
ER -