TY - JOUR
T1 - Test Chips with Scan-Based Logic Arrays
AU - Chen, Yu Hsiang
AU - Hsu, Chia Ming
AU - Lee, Kuen Jong
N1 - Funding Information:
Manuscript received January 31, 2020; revised May 4, 2020; accepted June 25, 2020. Date of publication July 20, 2020; date of current version March 19, 2021. This work was supported in part by the Ministry of Science and Technology of Taiwan under Contract 106-2221-E-006-229-MY3. This article was recommended by Associate Editor X. Li. (Corresponding author: Kuen-Jong Lee.) The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: holytak5690@ gmail.com; jjet4129889@gmail.com; kjlee@mail.ncku.edu.tw). Digital Object Identifier 10.1109/TCAD.2020.3010478
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2021/4
Y1 - 2021/4
N2 - This article proposes a scan-based test chip architecture targeting the diagnosis of multiple faults consisting of input pattern faults, stuck-at faults, and bridging faults (BFs). The architecture consists of a 2-D array of logic blocks and two sets of scan chains isolating the logic blocks. The scan chains are used to fully control and observe the logic blocks so as to enhance the testability and diagnosability of test chips. An efficient diagnostic procedure composed of two tests is developed to carry out the defect diagnosis process. Evaluation results show that the proposed procedure can always achieve 100% accuracy for single faults. When double faults containing 0, 1, and 2 BFs are considered, the proposed procedure can achieve 100% accuracy for 99.38%, 98.398%, and 97.416% of the faults and achieve perfect resolution for 98.81%, 98.006%, and 97.202% of the faults, respectively. Moreover, no matter how many faults exist, as long as no fault affects the scan registers, the proposed procedure can report all faulty logic blocks.
AB - This article proposes a scan-based test chip architecture targeting the diagnosis of multiple faults consisting of input pattern faults, stuck-at faults, and bridging faults (BFs). The architecture consists of a 2-D array of logic blocks and two sets of scan chains isolating the logic blocks. The scan chains are used to fully control and observe the logic blocks so as to enhance the testability and diagnosability of test chips. An efficient diagnostic procedure composed of two tests is developed to carry out the defect diagnosis process. Evaluation results show that the proposed procedure can always achieve 100% accuracy for single faults. When double faults containing 0, 1, and 2 BFs are considered, the proposed procedure can achieve 100% accuracy for 99.38%, 98.398%, and 97.416% of the faults and achieve perfect resolution for 98.81%, 98.006%, and 97.202% of the faults, respectively. Moreover, no matter how many faults exist, as long as no fault affects the scan registers, the proposed procedure can report all faulty logic blocks.
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U2 - 10.1109/TCAD.2020.3010478
DO - 10.1109/TCAD.2020.3010478
M3 - Article
AN - SCOPUS:85103343352
VL - 40
SP - 790
EP - 802
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 4
M1 - 9144517
ER -