Test Chips with Scan-Based Logic Arrays

Yu Hsiang Chen, Chia Ming Hsu, Kuen Jong Lee

Research output: Contribution to journalArticlepeer-review

Abstract

This article proposes a scan-based test chip architecture targeting the diagnosis of multiple faults consisting of input pattern faults, stuck-at faults, and bridging faults (BFs). The architecture consists of a 2-D array of logic blocks and two sets of scan chains isolating the logic blocks. The scan chains are used to fully control and observe the logic blocks so as to enhance the testability and diagnosability of test chips. An efficient diagnostic procedure composed of two tests is developed to carry out the defect diagnosis process. Evaluation results show that the proposed procedure can always achieve 100% accuracy for single faults. When double faults containing 0, 1, and 2 BFs are considered, the proposed procedure can achieve 100% accuracy for 99.38%, 98.398%, and 97.416% of the faults and achieve perfect resolution for 98.81%, 98.006%, and 97.202% of the faults, respectively. Moreover, no matter how many faults exist, as long as no fault affects the scan registers, the proposed procedure can report all faulty logic blocks.

Original languageEnglish
Article number9144517
Pages (from-to)790-802
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume40
Issue number4
DOIs
Publication statusPublished - 2021 Apr

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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