Test compression with single-input data spreader and multiple test sessions

Chang Wen Chen, Yi Cheng Kong, Kuen Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Test time and test data volume required to test modern integrated circuits grow rapidly with circuit complexity. Test compression is now widely used in industry to reduce test cost. In this paper, a simple yet highly efficient test data compression technique with small area overhead is presented. Efficient algorithms are developed to determine configurations of the test decompressor and corresponding test patterns in multiple test sessions. These algorithms result in higher test compression ratio and lower test application time with less CPU runtime compared to the latest previous work. Experimental results on IWLS'05 benchmark circuits show that on average we can increase the compression factor by 17.26%, decrease the test application time by 12.28% and cut down the CPU time by 42.92%, with only slight increase of area overhead. More importantly, up to 1500x test compression factor is achieved for a design containing about 2M gates, with only 0.1% area overhead.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781538624364
Publication statusPublished - 2018 Jan 24
Event26th IEEE Asian Test Symposium, ATS 2017 - Taipei, Taiwan
Duration: 2017 Nov 272017 Nov 30

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Other26th IEEE Asian Test Symposium, ATS 2017

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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