Abstract
Test time and test data volume required to test modern integrated circuits grow rapidly with circuit complexity. Test compression is now widely used in industry to reduce test cost. In this paper, a simple yet highly efficient test data compression technique with small area overhead is presented. Efficient algorithms are developed to determine configurations of the test decompressor and corresponding test patterns in multiple test sessions. These algorithms result in higher test compression ratio and lower test application time with less CPU runtime compared to the latest previous work. Experimental results on IWLS'05 benchmark circuits show that on average we can increase the compression factor by 17.26%, decrease the test application time by 12.28% and cut down the CPU time by 42.92%, with only slight increase of area overhead. More importantly, up to 1500x test compression factor is achieved for a design containing about 2M gates, with only 0.1% area overhead.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017 |
| Publisher | IEEE Computer Society |
| Pages | 24-29 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781538624364 |
| DOIs | |
| Publication status | Published - 2018 Jan 24 |
| Event | 26th IEEE Asian Test Symposium, ATS 2017 - Taipei, Taiwan Duration: 2017 Nov 27 → 2017 Nov 30 |
Publication series
| Name | Proceedings of the Asian Test Symposium |
|---|---|
| ISSN (Print) | 1081-7735 |
Other
| Other | 26th IEEE Asian Test Symposium, ATS 2017 |
|---|---|
| Country | Taiwan |
| City | Taipei |
| Period | 17-11-27 → 17-11-30 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Test compression with single-input data spreader and multiple test sessions. / Chen, Chang Wen; Kong, Yi Cheng; Lee, Kuen-Jong.
Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. IEEE Computer Society, 2018. p. 24-29 (Proceedings of the Asian Test Symposium).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Test compression with single-input data spreader and multiple test sessions
AU - Chen, Chang Wen
AU - Kong, Yi Cheng
AU - Lee, Kuen-Jong
PY - 2018/1/24
Y1 - 2018/1/24
N2 - Test time and test data volume required to test modern integrated circuits grow rapidly with circuit complexity. Test compression is now widely used in industry to reduce test cost. In this paper, a simple yet highly efficient test data compression technique with small area overhead is presented. Efficient algorithms are developed to determine configurations of the test decompressor and corresponding test patterns in multiple test sessions. These algorithms result in higher test compression ratio and lower test application time with less CPU runtime compared to the latest previous work. Experimental results on IWLS'05 benchmark circuits show that on average we can increase the compression factor by 17.26%, decrease the test application time by 12.28% and cut down the CPU time by 42.92%, with only slight increase of area overhead. More importantly, up to 1500x test compression factor is achieved for a design containing about 2M gates, with only 0.1% area overhead.
AB - Test time and test data volume required to test modern integrated circuits grow rapidly with circuit complexity. Test compression is now widely used in industry to reduce test cost. In this paper, a simple yet highly efficient test data compression technique with small area overhead is presented. Efficient algorithms are developed to determine configurations of the test decompressor and corresponding test patterns in multiple test sessions. These algorithms result in higher test compression ratio and lower test application time with less CPU runtime compared to the latest previous work. Experimental results on IWLS'05 benchmark circuits show that on average we can increase the compression factor by 17.26%, decrease the test application time by 12.28% and cut down the CPU time by 42.92%, with only slight increase of area overhead. More importantly, up to 1500x test compression factor is achieved for a design containing about 2M gates, with only 0.1% area overhead.
UR - http://www.scopus.com/inward/record.url?scp=85045193996&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85045193996&partnerID=8YFLogxK
U2 - 10.1109/ATS.2017.18
DO - 10.1109/ATS.2017.18
M3 - Conference contribution
AN - SCOPUS:85045193996
T3 - Proceedings of the Asian Test Symposium
SP - 24
EP - 29
BT - Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017
PB - IEEE Computer Society
ER -