Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Kai Li Wang, Bing Yang Lin, Cheng Wen Wu, Mincent Lee, Hao Chen, Hung Chih Lin, Ching Nen Peng, Min Jer Wang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, the authors propose a cost model for InFO WLCSP, which can be used for analyzing the total test cost with respect to the test configuration and for optimizing the test configuration and procedure. - Jin-Fu Li, National Central University.

Original languageEnglish
Article number7464303
Pages (from-to)50-58
Number of pages9
JournalIEEE Design and Test
Volume34
Issue number3
DOIs
Publication statusPublished - 2017 Jun 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Wang, K. L., Lin, B. Y., Wu, C. W., Lee, M., Chen, H., Lin, H. C., Peng, C. N., & Wang, M. J. (2017). Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Design and Test, 34(3), 50-58. [7464303]. https://doi.org/10.1109/MDAT.2016.2562060