Test efficiency analysis and improvement of SOC test platforms

Tong Yu Hsieh, Kuen-Jong Lee, Jian Jhih You

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Employing a test platform in an SOC design has been shown to be an effective method for SOC testing. However the test efficiency problem of a test platform has not been addressed. In this paper, we formally analyze the test efficiency of test platforms and seek for its optimization. We formulate the required numbers of test cycles for test platforms implemented with different test structures and/or executed with different test procedures. It is shown that up to 24X test time difference for platforms with different test structures/procedures is possible. Based on the derived formula, an appropriate test platform that can achieve best test efficiency with minimal area overhead can be determined.

Original languageEnglish
Title of host publicationProceedings of the 16th Asian Test Symposium, ATS 2007
Pages463-466
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event16th Asian Test Symposium, ATS 2007 - Beijing, China
Duration: 2007 Oct 82007 Oct 11

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other16th Asian Test Symposium, ATS 2007
CountryChina
CityBeijing
Period07-10-0807-10-11

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Hsieh, T. Y., Lee, K-J., & You, J. J. (2007). Test efficiency analysis and improvement of SOC test platforms. In Proceedings of the 16th Asian Test Symposium, ATS 2007 (pp. 463-466). [4388055] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2007.4388055