Test generation for open and delay faults in CMOS circuits

Cheng Hung Wu, Kuen Jong Lee, Sudhakar M. Reddy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the total test generation time can be reduced and very compact (small) test sets can be obtained. In addition, we present a path-based test generation method that aims to choose the smallest set of paths to cover all faults and each path tends to have the largest delay in the CMOS cell containing it. Using this method one can generate tests with better quality without increasing the number of test patterns. Experimental results show that on average 1.28X (1.35X) of the number of test patterns for transition delay faults are sufficient to detect all open and delay faults in CMOS cells as well as the transition faults in gate interconnects of ISCAS'89 (IWLS'05) circuits.

Original languageEnglish
Title of host publicationITC-Asia 2017 - International Test Conference in Asia
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages21-26
Number of pages6
ISBN (Electronic)9781538630518
DOIs
Publication statusPublished - 2017 Nov 3
Event1st International Test Conference in Asia, ITC-Asia 2017 - Taipei, Taiwan
Duration: 2017 Sep 132017 Sep 15

Publication series

NameITC-Asia 2017 - International Test Conference in Asia

Other

Other1st International Test Conference in Asia, ITC-Asia 2017
CountryTaiwan
CityTaipei
Period17-09-1317-09-15

Fingerprint

Networks (circuits)
Dynamic models
Transistors
Wire

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Automotive Engineering
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Wu, C. H., Lee, K. J., & Reddy, S. M. (2017). Test generation for open and delay faults in CMOS circuits. In ITC-Asia 2017 - International Test Conference in Asia (pp. 21-26). [8097104] (ITC-Asia 2017 - International Test Conference in Asia). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-ASIA.2017.8097104
Wu, Cheng Hung ; Lee, Kuen Jong ; Reddy, Sudhakar M. / Test generation for open and delay faults in CMOS circuits. ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 21-26 (ITC-Asia 2017 - International Test Conference in Asia).
@inproceedings{7f7003d1289341c7998bfc1a062eebb3,
title = "Test generation for open and delay faults in CMOS circuits",
abstract = "This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the total test generation time can be reduced and very compact (small) test sets can be obtained. In addition, we present a path-based test generation method that aims to choose the smallest set of paths to cover all faults and each path tends to have the largest delay in the CMOS cell containing it. Using this method one can generate tests with better quality without increasing the number of test patterns. Experimental results show that on average 1.28X (1.35X) of the number of test patterns for transition delay faults are sufficient to detect all open and delay faults in CMOS cells as well as the transition faults in gate interconnects of ISCAS'89 (IWLS'05) circuits.",
author = "Wu, {Cheng Hung} and Lee, {Kuen Jong} and Reddy, {Sudhakar M.}",
year = "2017",
month = "11",
day = "3",
doi = "10.1109/ITC-ASIA.2017.8097104",
language = "English",
series = "ITC-Asia 2017 - International Test Conference in Asia",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "21--26",
booktitle = "ITC-Asia 2017 - International Test Conference in Asia",
address = "United States",

}

Wu, CH, Lee, KJ & Reddy, SM 2017, Test generation for open and delay faults in CMOS circuits. in ITC-Asia 2017 - International Test Conference in Asia., 8097104, ITC-Asia 2017 - International Test Conference in Asia, Institute of Electrical and Electronics Engineers Inc., pp. 21-26, 1st International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, 17-09-13. https://doi.org/10.1109/ITC-ASIA.2017.8097104

Test generation for open and delay faults in CMOS circuits. / Wu, Cheng Hung; Lee, Kuen Jong; Reddy, Sudhakar M.

ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., 2017. p. 21-26 8097104 (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Test generation for open and delay faults in CMOS circuits

AU - Wu, Cheng Hung

AU - Lee, Kuen Jong

AU - Reddy, Sudhakar M.

PY - 2017/11/3

Y1 - 2017/11/3

N2 - This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the total test generation time can be reduced and very compact (small) test sets can be obtained. In addition, we present a path-based test generation method that aims to choose the smallest set of paths to cover all faults and each path tends to have the largest delay in the CMOS cell containing it. Using this method one can generate tests with better quality without increasing the number of test patterns. Experimental results show that on average 1.28X (1.35X) of the number of test patterns for transition delay faults are sufficient to detect all open and delay faults in CMOS cells as well as the transition faults in gate interconnects of ISCAS'89 (IWLS'05) circuits.

AB - This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the total test generation time can be reduced and very compact (small) test sets can be obtained. In addition, we present a path-based test generation method that aims to choose the smallest set of paths to cover all faults and each path tends to have the largest delay in the CMOS cell containing it. Using this method one can generate tests with better quality without increasing the number of test patterns. Experimental results show that on average 1.28X (1.35X) of the number of test patterns for transition delay faults are sufficient to detect all open and delay faults in CMOS cells as well as the transition faults in gate interconnects of ISCAS'89 (IWLS'05) circuits.

UR - http://www.scopus.com/inward/record.url?scp=85040562841&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85040562841&partnerID=8YFLogxK

U2 - 10.1109/ITC-ASIA.2017.8097104

DO - 10.1109/ITC-ASIA.2017.8097104

M3 - Conference contribution

AN - SCOPUS:85040562841

T3 - ITC-Asia 2017 - International Test Conference in Asia

SP - 21

EP - 26

BT - ITC-Asia 2017 - International Test Conference in Asia

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Wu CH, Lee KJ, Reddy SM. Test generation for open and delay faults in CMOS circuits. In ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc. 2017. p. 21-26. 8097104. (ITC-Asia 2017 - International Test Conference in Asia). https://doi.org/10.1109/ITC-ASIA.2017.8097104