Test integration for SOC supporting very low-cost testers

Chun Chuan Chi, Chih Yen Lo, Te Wen Ko, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

To reduce test cost for SOC products, it is important to reduce the cost of testers. When using low-cost testers which have a limited test bandwidth to perform testing, Built-In-Self-Test (BIST) is necessary to reduce the data volume to be transmitted between the tester and the device-under-test (DUT). We enhance the SOC test integration tool, STEAC, so that it can support SOCs containing BISTed cores which are to be tested by low-cost testers. A test chip is implemented to verify the proposed technique. Experimental results show that the enhanced STEAC successfully works with the HOY wireless test system and other low-cost testers.

Original languageEnglish
Title of host publicationProceedings of the 18th Asian Test Symposium, ATS 2009
Pages287-292
Number of pages6
DOIs
Publication statusPublished - 2009 Dec 1
Event18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
Duration: 2009 Nov 232009 Nov 26

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other18th Asian Test Symposium, ATS 2009
CountryTaiwan
CityTaichung
Period09-11-2309-11-26

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Chi, C. C., Lo, C. Y., Ko, T. W., & Wu, C. W. (2009). Test integration for SOC supporting very low-cost testers. In Proceedings of the 18th Asian Test Symposium, ATS 2009 (pp. 287-292). [5359330] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2009.51