Test pattern generation and clock disabling for simultaneous test time and power reduction

Jih Jeen Chen, Chia Kai Yang, Kuen-Jong Lee

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

Scan-based design has been widely used to transport test patterns in a system-on-a-chip (SOC) test architecture. Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly modifying and integrating a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results for the International Symposium on Circuits and Systems (ISCAS)'85 and '89 benchmark circuits show that significant reduction on both test application time and power dissipation can be achieved compared to the conventional scan method.

Original languageEnglish
Pages (from-to)363-369
Number of pages7
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume22
Issue number3
DOIs
Publication statusPublished - 2003 Mar 1

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Clocks
Energy dissipation
Networks (circuits)
Electric power utilization
Testing

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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Test pattern generation and clock disabling for simultaneous test time and power reduction. / Chen, Jih Jeen; Yang, Chia Kai; Lee, Kuen-Jong.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 3, 01.03.2003, p. 363-369.

Research output: Contribution to journalArticle

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