Testable and fault tolerant design for FFT networks

Jin Fu Li, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead-only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low-about 4% for 16-bit numbers regardless of the FFT network size.

Original languageEnglish
Title of host publicationProceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages201-209
Number of pages9
ISBN (Electronic)076950325X, 9780769503257
DOIs
Publication statusPublished - 1999 Jan 1
Event1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 - Albuquerque, United States
Duration: 1999 Nov 11999 Nov 3

Publication series

NameProceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

Conference

Conference1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
Country/TerritoryUnited States
CityAlbuquerque
Period99-11-0199-11-03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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