Testable and fault tolerant design for FFT networks

Jin Fu Li; Cheng Wen Wu

Testable and fault tolerant design for FFT networks

Jin Fu Li
, Cheng Wen Wu

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.

Original language	English
Pages (from-to)	201-209
Number of pages	9
Journal	IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Publication status	Published - 1999 Dec 1
Event	Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) - Albueqeurque, NM, USA Duration: 1999 Nov 1 → 1999 Nov 3

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@article{f8ea6d742681484a9c59605d7b42cc8e,

title = "Testable and fault tolerant design for FFT networks",

abstract = "We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100\% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4\% for 16-bit numbers regardless of the FFT network size.",

author = "Li, \{Jin Fu\} and Wu, \{Cheng Wen\}",

year = "1999",

month = dec,

day = "1",

language = "English",

pages = "201--209",

journal = "IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems",

issn = "1063-6722",

note = "Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) ; Conference date: 01-11-1999 Through 03-11-1999",

}

TY - JOUR

T1 - Testable and fault tolerant design for FFT networks

AU - Li, Jin Fu

AU - Wu, Cheng Wen

PY - 1999/12/1

Y1 - 1999/12/1

N2 - We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.

AB - We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.

UR - https://www.scopus.com/pages/publications/0033350061

UR - https://www.scopus.com/pages/publications/0033350061#tab=citedBy

M3 - Conference article

AN - SCOPUS:0033350061

SN - 1063-6722

SP - 201

EP - 209

JO - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

JF - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

T2 - Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99)

Y2 - 1 November 1999 through 3 November 1999

ER -

Testable and fault tolerant design for FFT networks

Abstract

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this