Testable design of bit-level systolic block FIR filters

Cheng Wen Wu; Jen Chuan Wang

doi:10.1109/ISCAS.1992.230328

Testable design of bit-level systolic block FIR filters

Cheng Wen Wu, Jen Chuan Wang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.

Original language	English
Title of host publication	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1129-1132
Number of pages	4
ISBN (Electronic)	0780305930
DOIs	https://doi.org/10.1109/ISCAS.1992.230328
Publication status	Published - 1992 Jan 1
Event	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States Duration: 1992 May 10 → 1992 May 13

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
ISSN (Print)	0271-4310

Conference

Conference	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Country	United States
City	San Diego
Period	92-05-10 → 92-05-13

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.1992.230328

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Cite this

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title = "Testable design of bit-level systolic block FIR filters",

abstract = "A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.",

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Wu, CW & Wang, JC 1992, Testable design of bit-level systolic block FIR filters. in 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992., 230328, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1129-1132, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992, San Diego, United States, 92-05-10. https://doi.org/10.1109/ISCAS.1992.230328

Testable design of bit-level systolic block FIR filters. / Wu, Cheng Wen; Wang, Jen Chuan.

1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1129-1132 230328 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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