Abstract
A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.
| Original language | English |
|---|---|
| Title of host publication | 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1129-1132 |
| Number of pages | 4 |
| ISBN (Electronic) | 0780305930 |
| DOIs | |
| Publication status | Published - 1992 Jan 1 |
| Event | 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States Duration: 1992 May 10 → 1992 May 13 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 3 |
| ISSN (Print) | 0271-4310 |
Conference
| Conference | 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 |
|---|---|
| Country | United States |
| City | San Diego |
| Period | 92-05-10 → 92-05-13 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Testable design of bit-level systolic block FIR filters. / Wu, Cheng Wen; Wang, Jen Chuan.
1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1129-1132 230328 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Testable design of bit-level systolic block FIR filters
AU - Wu, Cheng Wen
AU - Wang, Jen Chuan
PY - 1992/1/1
Y1 - 1992/1/1
N2 - A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.
AB - A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.
UR - http://www.scopus.com/inward/record.url?scp=33749761827&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33749761827&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.1992.230328
DO - 10.1109/ISCAS.1992.230328
M3 - Conference contribution
AN - SCOPUS:33749761827
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1129
EP - 1132
BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PB - Institute of Electrical and Electronics Engineers Inc.
ER -