TY - GEN
T1 - Testable design of bit-level systolic block FIR filters
AU - Wu, Cheng Wen
AU - Wang, Jen Chuan
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992/1/1
Y1 - 1992/1/1
N2 - A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.
AB - A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.
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U2 - 10.1109/ISCAS.1992.230328
DO - 10.1109/ISCAS.1992.230328
M3 - Conference contribution
AN - SCOPUS:33749761827
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1129
EP - 1132
BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Y2 - 10 May 1992 through 13 May 1992
ER -