Testable design of bit-level systolic block FIR filters

Cheng Wen Wu, Jen Chuan Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A design-for-testability approach for VLSI cellular arrays, based on our M-testability conditions, is applied to bit-level systolic block FTR filters. M- testability conditions guarantee 100% single-cell-fault testability with the minimum number of test patterns. We illustrate our approach on bit-level systolic arrays which implement block FTR filters, and show that a hardware overhead of no more than 5.6% is sufficient to make them M-testable. The resulting number of test patterns is only 32 for both the linear and 2-D filters, regardless of the filter order and block size.

Original languageEnglish
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1129-1132
Number of pages4
ISBN (Electronic)0780305930
DOIs
Publication statusPublished - 1992 Jan 1
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: 1992 May 101992 May 13

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period92-05-1092-05-13

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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