Testing for 3D FPGA interconnect open and short faults

Cheng-Wen Wu, Y.-L. Peng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publication3rd VLSI Test Technology Workshop (VTTW)
Place of PublicationNantou
Publication statusPublished - 2009 Jul

Cite this

Wu, C-W., & Peng, Y-L. (2009). Testing for 3D FPGA interconnect open and short faults. In 3rd VLSI Test Technology Workshop (VTTW)