Testing MRAM for write disturbance fault

Chin Lung Su; Chih Wea Tsai; Cheng Wen Wu; Chien Chung Hung; Young Shying Chen; Ming Jer Kao

doi:10.1109/TEST.2006.297702

Testing MRAM for write disturbance fault

Chin Lung Su, Chih Wea Tsai, Cheng Wen Wu, Chien Chung Hung, Young Shying Chen, Ming Jer Kao

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for Read/Write operations. It can also endure almost unlimited Read/Write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the Write Disturbance Fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the Write operation. The proposed WDF model is justified by chip measurement results. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. An MRAM chip has been designed and fabricated using a CMOS-based 0.18μm technology. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with March C-. Finally, we present a March 17N diagnosis algorithm for identifying the WDF.

Original language	English
Title of host publication	2006 IEEE International Test Conference, ITC
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	1424402921, 9781424402922
DOIs	https://doi.org/10.1109/TEST.2006.297702
Publication status	Published - 2007 Dec 1
Event	2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States Duration: 2006 Oct 22 → 2006 Oct 27

Publication series

Name	Proceedings - International Test Conference
ISSN (Print)	1089-3539

Conference

Conference	2006 IEEE International Test Conference, ITC
Country/Territory	United States
City	Santa Clara, CA
Period	06-10-22 → 06-10-27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/TEST.2006.297702

Cite this

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title = "Testing MRAM for write disturbance fault",

abstract = "The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for Read/Write operations. It can also endure almost unlimited Read/Write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the Write Disturbance Fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the Write operation. The proposed WDF model is justified by chip measurement results. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. An MRAM chip has been designed and fabricated using a CMOS-based 0.18μm technology. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with March C-. Finally, we present a March 17N diagnosis algorithm for identifying the WDF.",

author = "Su, {Chin Lung} and Tsai, {Chih Wea} and Wu, {Cheng Wen} and Hung, {Chien Chung} and Chen, {Young Shying} and Kao, {Ming Jer}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/TEST.2006.297702",

language = "English",

isbn = "1424402921",

series = "Proceedings - International Test Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2006 IEEE International Test Conference, ITC",

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note = "2006 IEEE International Test Conference, ITC ; Conference date: 22-10-2006 Through 27-10-2006",

}

Su, CL, Tsai, CW, Wu, CW, Hung, CC, Chen, YS & Kao, MJ 2007, Testing MRAM for write disturbance fault. in 2006 IEEE International Test Conference, ITC., 4079380, Proceedings - International Test Conference, Institute of Electrical and Electronics Engineers Inc., 2006 IEEE International Test Conference, ITC, Santa Clara, CA, United States, 06-10-22. https://doi.org/10.1109/TEST.2006.297702

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T1 - Testing MRAM for write disturbance fault

AU - Su, Chin Lung

AU - Tsai, Chih Wea

AU - Wu, Cheng Wen

AU - Hung, Chien Chung

AU - Chen, Young Shying

AU - Kao, Ming Jer

PY - 2007/12/1

Y1 - 2007/12/1

N2 - The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for Read/Write operations. It can also endure almost unlimited Read/Write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the Write Disturbance Fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the Write operation. The proposed WDF model is justified by chip measurement results. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. An MRAM chip has been designed and fabricated using a CMOS-based 0.18μm technology. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with March C-. Finally, we present a March 17N diagnosis algorithm for identifying the WDF.

AB - The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for Read/Write operations. It can also endure almost unlimited Read/Write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the Write Disturbance Fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the Write operation. The proposed WDF model is justified by chip measurement results. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. An MRAM chip has been designed and fabricated using a CMOS-based 0.18μm technology. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with March C-. Finally, we present a March 17N diagnosis algorithm for identifying the WDF.

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M3 - Conference contribution

SN - 1424402921

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T3 - Proceedings - International Test Conference

BT - 2006 IEEE International Test Conference, ITC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 IEEE International Test Conference, ITC

Y2 - 22 October 2006 through 27 October 2006

ER -

Testing MRAM for write disturbance fault

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