TY - GEN
T1 - TG-based technique for NBTI degradation and leakage optimization
AU - Lin, Chin Hung
AU - Lin, Ing Chao
AU - Li, Kuan Hui
PY - 2011
Y1 - 2011
N2 - NBTI (Negative Bias Temperature Instability), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Meanwhile, reducing leakage consumption has become major design goals. In this paper, we propose a novel transmission gate-based (TG) technique to minimize NBTI-induced degradation and leakage. This technique provides higher flexibility compared to the gate replacement technique. Simulation results show our proposed technique has up to 20X and 2.44X on average improvement on NBTI-induced degradation with comparable leakage power reduction. With a 19% area penalty, combining our technique and the gate replacement can reduce 19.39% of the total leakage power and 36.56% of the NBTI-induced circuit degradation.
AB - NBTI (Negative Bias Temperature Instability), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Meanwhile, reducing leakage consumption has become major design goals. In this paper, we propose a novel transmission gate-based (TG) technique to minimize NBTI-induced degradation and leakage. This technique provides higher flexibility compared to the gate replacement technique. Simulation results show our proposed technique has up to 20X and 2.44X on average improvement on NBTI-induced degradation with comparable leakage power reduction. With a 19% area penalty, combining our technique and the gate replacement can reduce 19.39% of the total leakage power and 36.56% of the NBTI-induced circuit degradation.
UR - http://www.scopus.com/inward/record.url?scp=80052738649&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80052738649&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2011.5993625
DO - 10.1109/ISLPED.2011.5993625
M3 - Conference contribution
AN - SCOPUS:80052738649
SN - 9781612846590
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 133
EP - 138
BT - IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
T2 - 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Y2 - 1 August 2011 through 3 August 2011
ER -