The delay vernier pattern generation technique

Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schafler, Ralph K. Cavin

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


The authors describe a new technique for generating an arbitrary digital data stream with very fine timing resolution. Note that this timing resolution specifies the output edge placement precision, not the bit rate. The resolution is determined by the difference between two propagation delays rather than by an absolute delay. Because this difference can be made very small, the circuit, called the delay vernier generator, can achieve unprecedented timing resolution in a particular circuit technology. Also, this very precise timing is obtained without requiring an extremely high speed clock. The generator architecture includes delay-locked loop calibration mechanisms to compensate for process and temperature variations. A prototype chip was fabricated in a l.2-μm CMOS technology, and measurements confirmed that resolutions as fine as 100 ps can be achieved reliably.

Original languageEnglish
Pages (from-to)551-562
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number4
Publication statusPublished - 1997 Apr

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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