TY - GEN
T1 - The design of a high-performance scalable architecture for image processing applications
AU - Gray, C. Thomas
AU - Liu, Wentai
AU - Hughes, Thomas
AU - Cavin, Ralph
PY - 1991
Y1 - 1991
N2 - The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each. The architecture is designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations. The interleaved memory system makes the architecture highly scalable in that L and P can be chosen to optimize performance for particular problems and reconfigurable in that, once L and P are fixed, problems of any size can still be mapped onto the architecture. The authors demonstrate techniques and methods for mapping computational structures to the architecture by considering the case of the 1-D butterfly network (1DBN). Since many other computational structures can be mapped to 1DBN, this gives a firm application base for the architecture. The authors also demonstrate methods for scheduling and controlling the memory system.
AB - The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each. The architecture is designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations. The interleaved memory system makes the architecture highly scalable in that L and P can be chosen to optimize performance for particular problems and reconfigurable in that, once L and P are fixed, problems of any size can still be mapped onto the architecture. The authors demonstrate techniques and methods for mapping computational structures to the architecture by considering the case of the 1-D butterfly network (1DBN). Since many other computational structures can be mapped to 1DBN, this gives a firm application base for the architecture. The authors also demonstrate methods for scheduling and controlling the memory system.
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M3 - Conference contribution
AN - SCOPUS:0025901565
SN - 0818690895
T3 - Proc 90 Int Conf Appl Specif Array Process
SP - 722
EP - 733
BT - Proc 90 Int Conf Appl Specif Array Process
PB - Publ by IEEE
T2 - Proceedings of the 1990 International Conference on Application Specific Array Processors
Y2 - 5 September 1990 through 7 September 1990
ER -