The design of a high-performance scalable architecture for image processing applications

C. Thomas Gray, Wentai Liu, Thomas Hughes, Ralph Cavin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each. The architecture is designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations. The interleaved memory system makes the architecture highly scalable in that L and P can be chosen to optimize performance for particular problems and reconfigurable in that, once L and P are fixed, problems of any size can still be mapped onto the architecture. The authors demonstrate techniques and methods for mapping computational structures to the architecture by considering the case of the 1-D butterfly network (1DBN). Since many other computational structures can be mapped to 1DBN, this gives a firm application base for the architecture. The authors also demonstrate methods for scheduling and controlling the memory system.

Original languageEnglish
Title of host publicationProc 90 Int Conf Appl Specif Array Process
PublisherPubl by IEEE
Pages722-733
Number of pages12
ISBN (Print)0818690895
Publication statusPublished - 1991
EventProceedings of the 1990 International Conference on Application Specific Array Processors - Princeton, NJ, USA
Duration: 1990 Sept 51990 Sept 7

Publication series

NameProc 90 Int Conf Appl Specif Array Process

Conference

ConferenceProceedings of the 1990 International Conference on Application Specific Array Processors
CityPrinceton, NJ, USA
Period90-09-0590-09-07

All Science Journal Classification (ASJC) codes

  • General Engineering

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