TY - GEN
T1 - The design of a vector-radix 2DFFT chip
AU - Liu, Wentai
AU - Duh, J. C.
AU - Atkins, Daniel E.
N1 - Publisher Copyright:
© 1985 IEEE.
PY - 1985
Y1 - 1985
N2 - Architectures based on the vector-radix 2DFFT algorithm and hence can avoid the matrix transpose problem have been proposed. The unique feature of the proposed architectures is that the data can be driven into the arithmetic processors in a pipeline fashion. This paper presents a propotype chip, which has been designed in 2 μm NMOS technology, for the generalized butterfly unit. The chip is a two-stage pipelined processor. The design experience, timing information, and the chip features including four multipliers, one adder/subtracter and PLA controllers are presented.
AB - Architectures based on the vector-radix 2DFFT algorithm and hence can avoid the matrix transpose problem have been proposed. The unique feature of the proposed architectures is that the data can be driven into the arithmetic processors in a pipeline fashion. This paper presents a propotype chip, which has been designed in 2 μm NMOS technology, for the generalized butterfly unit. The chip is a two-stage pipelined processor. The design experience, timing information, and the chip features including four multipliers, one adder/subtracter and PLA controllers are presented.
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U2 - 10.1109/ARITH.1985.6158962
DO - 10.1109/ARITH.1985.6158962
M3 - Conference contribution
AN - SCOPUS:84942392422
T3 - Proceedings - Symposium on Computer Arithmetic
SP - 231
EP - 236
BT - Proceedings - 7th Symposium on Computer Arithmetic, ARITH 1985
A2 - Hwang, Kai
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE Symposium on Computer Arithmetic, ARITH 1985
Y2 - 4 June 1985 through 6 June 1985
ER -