The effect of geometry on the noise characterization of SiGe HBTs and optimized device sizes for the design of low-noise amplifiers

Chien Hsun Lin; Yan Kuin Su; Ying Zong Juang; Ricky W. Chuang; Shoou Jinn Chang; Jone F. Chen; Chih Ho Tu

doi:10.1109/TMTT.2004.834179

The effect of geometry on the noise characterization of SiGe HBTs and optimized device sizes for the design of low-noise amplifiers

Chien Hsun Lin, Yan Kuin Su, Ying Zong Juang, Ricky W. Chuang, Shoou Jinn Chang, Jone F. Chen, Chih Ho Tu

Institute of Microelectronics

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

The impacts of various layout configuration and device dimensions on device performance are examined. The geometrical scaling issues including emitter length and emitter stripe-number scaling are used to shift simultaneously the optimum noise and optimum source impedance to a point that is close to 50 Ω. Via this method, not only is the optimal transistor size for low-noise applications obtained, but the matching network is simplified to reduce the losses of passive networks and the chip area. Based on experimental results, optimum SiGe HBTs and bias suitable for low-noise amplifiers (LNAs) are determined. Via the comparison of the state-of-the-art SiGe LNAs, it is confirmed that this method is effective to obtain better performances. Using the same method, the optimum device size at any bias and any frequency for low-noise applications can also be achieved.

Original language	English
Pages (from-to)	2153-2162
Number of pages	10
Journal	IEEE Transactions on Microwave Theory and Techniques
Volume	52
Issue number	9 I
DOIs	https://doi.org/10.1109/TMTT.2004.834179
Publication status	Published - 2004 Sept

All Science Journal Classification (ASJC) codes

Radiation
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/TMTT.2004.834179

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title = "The effect of geometry on the noise characterization of SiGe HBTs and optimized device sizes for the design of low-noise amplifiers",

abstract = "The impacts of various layout configuration and device dimensions on device performance are examined. The geometrical scaling issues including emitter length and emitter stripe-number scaling are used to shift simultaneously the optimum noise and optimum source impedance to a point that is close to 50 Ω. Via this method, not only is the optimal transistor size for low-noise applications obtained, but the matching network is simplified to reduce the losses of passive networks and the chip area. Based on experimental results, optimum SiGe HBTs and bias suitable for low-noise amplifiers (LNAs) are determined. Via the comparison of the state-of-the-art SiGe LNAs, it is confirmed that this method is effective to obtain better performances. Using the same method, the optimum device size at any bias and any frequency for low-noise applications can also be achieved.",

author = "Lin, {Chien Hsun} and Su, {Yan Kuin} and Juang, {Ying Zong} and Chuang, {Ricky W.} and Chang, {Shoou Jinn} and Chen, {Jone F.} and Tu, {Chih Ho}",

note = "Funding Information: Manuscript received October 25, 2003; revised March 9, 2004. This work was supported in part by the National Science Council, Taiwan, R.O.C., under Grant NSC 92-2218-E-006-039.",

year = "2004",

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doi = "10.1109/TMTT.2004.834179",

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AU - Lin, Chien Hsun

AU - Su, Yan Kuin

AU - Juang, Ying Zong

AU - Chuang, Ricky W.

AU - Chang, Shoou Jinn

AU - Chen, Jone F.

AU - Tu, Chih Ho

N1 - Funding Information: Manuscript received October 25, 2003; revised March 9, 2004. This work was supported in part by the National Science Council, Taiwan, R.O.C., under Grant NSC 92-2218-E-006-039.

PY - 2004/9

Y1 - 2004/9

N2 - The impacts of various layout configuration and device dimensions on device performance are examined. The geometrical scaling issues including emitter length and emitter stripe-number scaling are used to shift simultaneously the optimum noise and optimum source impedance to a point that is close to 50 Ω. Via this method, not only is the optimal transistor size for low-noise applications obtained, but the matching network is simplified to reduce the losses of passive networks and the chip area. Based on experimental results, optimum SiGe HBTs and bias suitable for low-noise amplifiers (LNAs) are determined. Via the comparison of the state-of-the-art SiGe LNAs, it is confirmed that this method is effective to obtain better performances. Using the same method, the optimum device size at any bias and any frequency for low-noise applications can also be achieved.

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The effect of geometry on the noise characterization of SiGe HBTs and optimized device sizes for the design of low-noise amplifiers

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