The influence of the layout on the ESD performance Of HV-LDMOS

Jian Hsing Lee, Hung Der Su, Chien Ling Chan, D. H. Yang, Jone F. Chen, K. M. Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.

Original languageEnglish
Title of host publication2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010
Pages303-306
Number of pages4
Publication statusPublished - 2010 Sep 20
Event2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010 - Hiroshima, Japan
Duration: 2010 Jun 62010 Jun 10

Publication series

NameProceedings of the International Symposium on Power Semiconductor Devices and ICs
ISSN (Print)1063-6854

Other

Other2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010
CountryJapan
CityHiroshima
Period10-06-0610-06-10

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Lee, J. H., Su, H. D., Chan, C. L., Yang, D. H., Chen, J. F., & Wu, K. M. (2010). The influence of the layout on the ESD performance Of HV-LDMOS. In 2010 22nd International Symposium on Power Semiconductor Devices and IC's, ISPSD 2010 (pp. 303-306). [5543900] (Proceedings of the International Symposium on Power Semiconductor Devices and ICs).