The new architecture of Chinese abacus multiplier

Chien Hung Lin, Yun Fu Huang, Der Her Lee, Pao Hua Liao, Chih Wei Hsu

Research output: Contribution to journalArticlepeer-review

Abstract

This study demonstrated a 4×4 bits multiplier that was based on the Chinese abacus. Comparing the simulation results of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, this 4×4 bits abacus multiplier showed a 19.7% and 10.6% delay improvement in 0.35μm and 0.18μm technology respectively than that of the 4×4 bits Braun array multiplier, while power consumption of the 4×4 bits abacus multiplier was 8.7% and 18% lower respectively.The performance: power-consumption*delay of the abacus multiplier is respectively,less about 23.2% and 23.5% also.

Original languageEnglish
Pages (from-to)593-603
Number of pages11
JournalWSEAS Transactions on Computers
Volume9
Issue number6
Publication statusPublished - 2010 Jun

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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