The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Mehmet R. Yuce, Wentai Liu, Bhaskar Bharat, John Damiano, Paul D. Franzon

Research output: Contribution to journalConference articlepeer-review

3 Citations (Scopus)

Abstract

A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

Original languageEnglish
Pages (from-to)591-594
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 2004
EventProceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States
Duration: 2004 Oct 32004 Oct 6

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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