The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Mehmet R. Yuce; Wentai Liu; Bhaskar Bharat; John Damiano; Paul D. Franzon

The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Mehmet R. Yuce, Wentai Liu, Bhaskar Bharat, John Damiano, Paul D. Franzon

Department of Biomedical Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

Original language	English
Pages (from-to)	591-594
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 2004
Event	Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States Duration: 2004 Oct 3 → 2004 Oct 6

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers",

abstract = "A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.",

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note = "Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC ; Conference date: 03-10-2004 Through 06-10-2004",

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T1 - The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

AU - Yuce, Mehmet R.

AU - Liu, Wentai

AU - Bharat, Bhaskar

AU - Damiano, John

AU - Franzon, Paul D.

PY - 2004

Y1 - 2004

N2 - A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

AB - A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm Silicon On Insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 Kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

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M3 - Conference article

AN - SCOPUS:17044382569

SN - 0886-5930

SP - 591

EP - 594

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC

Y2 - 3 October 2004 through 6 October 2004

ER -

The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Abstract

All Science Journal Classification (ASJC) codes

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