The physics of Cu pillar bump interconnect under electromigration stress testing

Yu Hsiang Hsiao, Chien Fan Chen, Ping Feng Yang, Chang Chi Lee, Min Chi Liu, Kwang-Lung Lin, Chiao Wen Chen, Bradford J. Factor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The industry saw the transition of flip chip technology from lead free solder system to Cu pillar bump a few years ago. The risk of fail location under electromigration (EM) shifts from the solder/UBM interface of the standard solder bump to the solder joint of the Cu pillar solder joint. This study investigated the performance of the Cu pillar solder interconnect under current stress testing and temperature acceleration. The EM stress test of Cu pillar bumps interconnect was designed and implemented comparing the bump solder tips joined with OSP (organic solderability preservative)-Cu (the OSP-Cu bump) substrate and ENEPIG (electroless Ni(P)/electroless Pd/immersion Au)-Cu (the ENEPIG-Cu bump) substrate. The bumps with different solder volumes, 20 μm and 50 μm in height, were investigated for EM performance comparison. The EM testing was conducted at current density 7 kA/cm2 under various temperatures of 125 °C, 135 °C and 150 °C. The EM duration time of Cu pillar bump joints were estimated for testing up to 10000 hours. The joint with smaller solder volume tends to exhibit better EM life. The experimental results showed that the Cu pillar bumps on OSP-Cu performed superior to that on ENEPIG-Cu. The cross sectional microstructure analysis indicates that the intermetallic compound (IMC) formed are mainly Cu6Sn5 and Cu3Sn for the Cu pillar bump joint on OSP-Cu substrate, while (Au, Pd)Sn4 was also detected for the ENEPIG-Cu substrate. The failure analysis of the failed joints indicated that the failure behavior closely related to the volume of IMC formed and the IMC structure within the Cu pillar joint.

Original languageEnglish
Title of host publicationProceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479940264
DOIs
Publication statusPublished - 2014 Nov 18
Event5th Electronics System-Integration Technology Conference, ESTC 2014 - Helsinki, Finland
Duration: 2014 Sep 162014 Sep 18

Publication series

NameProceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014

Other

Other5th Electronics System-Integration Technology Conference, ESTC 2014
CountryFinland
CityHelsinki
Period14-09-1614-09-18

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Hsiao, Y. H., Chen, C. F., Yang, P. F., Lee, C. C., Liu, M. C., Lin, K-L., Chen, C. W., & Factor, B. J. (2014). The physics of Cu pillar bump interconnect under electromigration stress testing. In Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014 [6962759] (Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESTC.2014.6962759