The study of sensitive circuit and layout for CDM improvement

Jian Hsing Lee; J. R. Shih; Shawn Guo; Dao Hong Yang; Jone F. Chen; David Su; Kenneth Wu

doi:10.1109/IPFA.2009.5232664

The study of sensitive circuit and layout for CDM improvement

Jian Hsing Lee, J. R. Shih, Shawn Guo, Dao Hong Yang, Jone F. Chen, David Su, Kenneth Wu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.

Original language	English
Title of host publication	Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009
Pages	228-232
Number of pages	5
DOIs	https://doi.org/10.1109/IPFA.2009.5232664
Publication status	Published - 2009 Nov 16
Event	2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009 - Suzhou, China Duration: 2009 Jul 6 → 2009 Jul 10

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other	2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009
Country/Territory	China
City	Suzhou
Period	09-07-06 → 09-07-10

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/IPFA.2009.5232664

Cite this

Lee, J. H., Shih, J. R., Guo, S., Yang, D. H., Chen, J. F., Su, D., & Wu, K. (2009). The study of sensitive circuit and layout for CDM improvement. In Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009 (pp. 228-232). [5232664] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2009.5232664

Lee, Jian Hsing ; Shih, J. R. ; Guo, Shawn et al. / The study of sensitive circuit and layout for CDM improvement. Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009. 2009. pp. 228-232 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{b118e46d6fde433eb0c4e93052460608,

title = "The study of sensitive circuit and layout for CDM improvement",

abstract = "The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.",

author = "Lee, {Jian Hsing} and Shih, {J. R.} and Shawn Guo and Yang, {Dao Hong} and Chen, {Jone F.} and David Su and Kenneth Wu",

year = "2009",

month = nov,

day = "16",

doi = "10.1109/IPFA.2009.5232664",

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series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

pages = "228--232",

booktitle = "Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009",

note = "2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009 ; Conference date: 06-07-2009 Through 10-07-2009",

}

Lee, JH, Shih, JR, Guo, S, Yang, DH, Chen, JF, Su, D & Wu, K 2009, The study of sensitive circuit and layout for CDM improvement. in Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009., 5232664, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, pp. 228-232, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009, Suzhou, China, 09-07-06. https://doi.org/10.1109/IPFA.2009.5232664

The study of sensitive circuit and layout for CDM improvement. / Lee, Jian Hsing; Shih, J. R.; Guo, Shawn et al.
Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009. 2009. p. 228-232 5232664 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Su, David

AU - Wu, Kenneth

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AB - The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.

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Lee JH, Shih JR, Guo S, Yang DH, Chen JF, Su D et al. The study of sensitive circuit and layout for CDM improvement. In Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009. 2009. p. 228-232. 5232664. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2009.5232664

The study of sensitive circuit and layout for CDM improvement

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