To keep pursuing the chip resistance capacitance (RC) delay improvement, it is necessary to further reduce k value. Accordingly, direct polished porous type ultra-low-k(ULK) film instead of non-porous low-k materials is integrated into Cu interconnects from 45 nm. However, because of the ULK characteristics and the minimized feature size, the time-to-break-down (TDDB) failure mode behaves different from silica glass or non-porous low-k film. And it is not only sensitive to geometries but also very sensitive to the engineering in the fabrication process. In this paper, we identified three TDDB failure modes, Cu protrusion from trench top interface, sidewall, and bottom corner, in the direct polished ULK scheme. In addition, on the basis of those failure modes, the related mechanisms in conjunction with the sensitivity to the processes are reported as well.