In order to realize the high performance of RC delay, direct polished porous type ultra low-K film (ULK) is integrated into Cu dual-damascene interconnects for 45 nm and beyond. In the past, metal line seems not an important role in the world of TDDB. However, because of the minimized feature size and the relative fragile ULK film properties, it was found that the Cu roughness of polished surface also plays an important role to effect on the reliability such as TDDB from this generation, [1, 2]. Post-cleaning of Cu CMP is a major process to manage the Cu surface roughness. In this paper, the correlation for post-cleaning time to the TDDB was discussed. The mechanism with two models was built up to explain this behavior as well.