Abstract
The advancement of very large scale integration (VLSI) techniques has overcome some computation bottlenecks in computer applications, and resulted in improved execution speeds. This paper applies VLSI techniques to state estimation matrix triangulation enhancement in power systems. The systolic array processor is used with a dedicated structure for implementation. The proposed configuration is depicted and described. For different but compatible numerical types, the intermediate processor is taken into account. The proposed method improves the computation speed with high potential for application to many power system problems. Simulations and comparisons of the proposed method with the conventional method support the better characteristics of the systolic array for state estimation.
| Original language | English |
|---|---|
| Pages (from-to) | 191-196 |
| Number of pages | 6 |
| Journal | Electric Power Systems Research |
| Volume | 13 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 1987 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering
Cite this
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The VLSI technique for state estimation enhancement in power systems. / Lin, Chin-E.; Huang, Shyh-Jier.
In: Electric Power Systems Research, Vol. 13, No. 3, 01.01.1987, p. 191-196.Research output: Contribution to journal › Article
TY - JOUR
T1 - The VLSI technique for state estimation enhancement in power systems
AU - Lin, Chin-E.
AU - Huang, Shyh-Jier
PY - 1987/1/1
Y1 - 1987/1/1
N2 - The advancement of very large scale integration (VLSI) techniques has overcome some computation bottlenecks in computer applications, and resulted in improved execution speeds. This paper applies VLSI techniques to state estimation matrix triangulation enhancement in power systems. The systolic array processor is used with a dedicated structure for implementation. The proposed configuration is depicted and described. For different but compatible numerical types, the intermediate processor is taken into account. The proposed method improves the computation speed with high potential for application to many power system problems. Simulations and comparisons of the proposed method with the conventional method support the better characteristics of the systolic array for state estimation.
AB - The advancement of very large scale integration (VLSI) techniques has overcome some computation bottlenecks in computer applications, and resulted in improved execution speeds. This paper applies VLSI techniques to state estimation matrix triangulation enhancement in power systems. The systolic array processor is used with a dedicated structure for implementation. The proposed configuration is depicted and described. For different but compatible numerical types, the intermediate processor is taken into account. The proposed method improves the computation speed with high potential for application to many power system problems. Simulations and comparisons of the proposed method with the conventional method support the better characteristics of the systolic array for state estimation.
UR - http://www.scopus.com/inward/record.url?scp=0023559291&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0023559291&partnerID=8YFLogxK
U2 - 10.1016/0378-7796(87)90004-6
DO - 10.1016/0378-7796(87)90004-6
M3 - Article
AN - SCOPUS:0023559291
VL - 13
SP - 191
EP - 196
JO - Electric Power Systems Research
JF - Electric Power Systems Research
SN - 0378-7796
IS - 3
ER -