TY - GEN
T1 - Theoretical analysis and implementation of a variable gain even harmonic mixer
AU - Hsieh, Jian Yu
AU - Lee, Shuenn-Yuh
PY - 2007/9/28
Y1 - 2007/9/28
N2 - This paper presents a new topology of variable gain even harmonic mixer (VGEHM) for IEEE 802.11a, which includes a proposed NMOS double frequency circuit (DFC) and a PMOS active load (AL) topology. The proposed NMOS DFC can immunize the DC offset and increase isolation. The AL is used to increase gain and achieve wide-gain variation. In this: paper, theoretical analyses of conversion gain and linearity have been described in detail. The proposed mixer is implemented in TSMC CMOS 0.18μm process to evaluate its performance. The measured results, according to RF of 5.25GHz and IF of 800KHz, show the isolation of 57.35dB between RF and LO, and the variable conversion gain between -28.02dB and 6.21dB. Meanwhile, the high linearity is also achieved by referring to input compression point (IP1dB) of-16dBm, input second order intercept point (IIP2) of 17.66dBm, input third order intercept point (IIP3) of -3.945dBm. Besides, low power dissipation of 7.2mW without buffer for 1.8V supply voltage is also achieved.
AB - This paper presents a new topology of variable gain even harmonic mixer (VGEHM) for IEEE 802.11a, which includes a proposed NMOS double frequency circuit (DFC) and a PMOS active load (AL) topology. The proposed NMOS DFC can immunize the DC offset and increase isolation. The AL is used to increase gain and achieve wide-gain variation. In this: paper, theoretical analyses of conversion gain and linearity have been described in detail. The proposed mixer is implemented in TSMC CMOS 0.18μm process to evaluate its performance. The measured results, according to RF of 5.25GHz and IF of 800KHz, show the isolation of 57.35dB between RF and LO, and the variable conversion gain between -28.02dB and 6.21dB. Meanwhile, the high linearity is also achieved by referring to input compression point (IP1dB) of-16dBm, input second order intercept point (IIP2) of 17.66dBm, input third order intercept point (IIP3) of -3.945dBm. Besides, low power dissipation of 7.2mW without buffer for 1.8V supply voltage is also achieved.
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U2 - 10.1109/VDAT.2007.372760
DO - 10.1109/VDAT.2007.372760
M3 - Conference contribution
AN - SCOPUS:34648830403
SN - 1424405831
SN - 9781424405831
T3 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
BT - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
T2 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Y2 - 25 April 2007 through 27 April 2007
ER -