Threshold tuning method for arrays of split-gate nanostructure transistors in series

  • Haider Al-Taie
  • , Luke W. Smith
  • , Reuben K. Puddy
  • , Patrick See
  • , Jonathan P. Griffiths
  • , Ian Farrer
  • , Geb A.C. Jones
  • , David A. Ritchie
  • , Charles G. Smith
  • , Michael J. Kelly

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a method to tune an arbitrary number of split-gate transistors in series to their threshold voltage, prior to initiating any particular experiment. The model accounts for device variations and considers coupled/uncoupled electrical gates and ballistic/ohmic addition of resistances. Experimental verification of this 'zeroing method' is provided by detailed conductance measurements through a two-dimensional electron gas formed in a GaAs/AlGaAs heterostructure with two split-gate transistors in series and is extended to zero an array of up to nine split gates in series.

Original languageEnglish
Title of host publicationProceedings of the IEEE Conference on Nanotechnology
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages490-493
Number of pages4
ISBN (Electronic)9781479956227
DOIs
Publication statusPublished - 2014 Nov 26
Event2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014 - Toronto, Canada
Duration: 2014 Aug 182014 Aug 21

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
ISSN (Electronic)1944-9399

Conference

Conference2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014
Country/TerritoryCanada
CityToronto
Period14-08-1814-08-21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modelling and Simulation
  • Instrumentation

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