Threshold-voltage variability analysis and modeling for junctionless double-gate transistors

Chun Yu Chen, Jyi Tsong Lin, Meng Hsueh Chiang

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

This paper presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10 nm or below, thickness variation becomes a significant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when TSi is less than 4 nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement.

Original languageEnglish
Pages (from-to)22-26
Number of pages5
JournalMicroelectronics Reliability
Volume74
DOIs
Publication statusPublished - 2017 Jul

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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