Token scan cell for low power testing

T. C. Huang, K. J. Lee

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved.

Original languageEnglish
Pages (from-to)678-679
Number of pages2
JournalElectronics Letters
Issue number11
Publication statusPublished - 2001 May 24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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