Abstract
A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved.
Original language | English |
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Pages (from-to) | 678-679 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 37 |
Issue number | 11 |
DOIs | |
Publication status | Published - 2001 May 24 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering