Token scan cell for low power testing

T. C. Huang; K. J. Lee

doi:10.1049/el:20010463

Token scan cell for low power testing

T. C. Huang, K. J. Lee

Department of Electrical Engineering

Research output: Contribution to journal › Article

5 Citations (Scopus)

Abstract

A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved.

Original language	English
Pages (from-to)	678-679
Number of pages	2
Journal	Electronics Letters
Volume	37
Issue number	11
DOIs	https://doi.org/10.1049/el:20010463
Publication status	Published - 2001 May 24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:20010463

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Huang, T. C., & Lee, K. J. (2001). Token scan cell for low power testing. Electronics Letters, 37(11), 678-679. https://doi.org/10.1049/el:20010463

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