Tolerance of performance degrading faults for effective yield improvement

Tong Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Citations (Scopus)


To provide a new avenue for improving yield for nanoscale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.

Original languageEnglish
Title of host publicationInternational Test Conference, ITC 2009 - Proceedings
Publication statusPublished - 2009 Dec 15
EventInternational Test Conference, ITC 2009 - Austin, TX, United States
Duration: 2009 Nov 12009 Nov 6

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


OtherInternational Test Conference, ITC 2009
Country/TerritoryUnited States
CityAustin, TX

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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