Tolerance of performance degrading faults for effective yield improvement

Tong Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Citations (Scopus)

Abstract

To provide a new avenue for improving yield for nanoscale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.

Original languageEnglish
Title of host publicationInternational Test Conference, ITC 2009 - Proceedings
DOIs
Publication statusPublished - 2009 Dec 15
EventInternational Test Conference, ITC 2009 - Austin, TX, United States
Duration: 2009 Nov 12009 Nov 6

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

OtherInternational Test Conference, ITC 2009
CountryUnited States
CityAustin, TX
Period09-11-0109-11-06

Fingerprint

Tolerance
Fault
Degradation
Clocks
Throughput
Fabrication
Binning
Chip
Branch Prediction
Unit
System Performance
Cycle
Decrease
Output
Experimental Results

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Hsieh, T. Y., Breuer, M. A., Annavaram, M., Gupta, S. K., & Lee, K-J. (2009). Tolerance of performance degrading faults for effective yield improvement. In International Test Conference, ITC 2009 - Proceedings [5355594] (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2009.5355594
Hsieh, Tong Yu ; Breuer, Melvin A. ; Annavaram, Murali ; Gupta, Sandeep K. ; Lee, Kuen-Jong. / Tolerance of performance degrading faults for effective yield improvement. International Test Conference, ITC 2009 - Proceedings. 2009. (Proceedings - International Test Conference).
@inproceedings{661d72af910a4863a5ba84270455499f,
title = "Tolerance of performance degrading faults for effective yield improvement",
abstract = "To provide a new avenue for improving yield for nanoscale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97{\%} of these faults induce almost no performance degradation.",
author = "Hsieh, {Tong Yu} and Breuer, {Melvin A.} and Murali Annavaram and Gupta, {Sandeep K.} and Kuen-Jong Lee",
year = "2009",
month = "12",
day = "15",
doi = "10.1109/TEST.2009.5355594",
language = "English",
isbn = "9781424448678",
series = "Proceedings - International Test Conference",
booktitle = "International Test Conference, ITC 2009 - Proceedings",

}

Hsieh, TY, Breuer, MA, Annavaram, M, Gupta, SK & Lee, K-J 2009, Tolerance of performance degrading faults for effective yield improvement. in International Test Conference, ITC 2009 - Proceedings., 5355594, Proceedings - International Test Conference, International Test Conference, ITC 2009, Austin, TX, United States, 09-11-01. https://doi.org/10.1109/TEST.2009.5355594

Tolerance of performance degrading faults for effective yield improvement. / Hsieh, Tong Yu; Breuer, Melvin A.; Annavaram, Murali; Gupta, Sandeep K.; Lee, Kuen-Jong.

International Test Conference, ITC 2009 - Proceedings. 2009. 5355594 (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Tolerance of performance degrading faults for effective yield improvement

AU - Hsieh, Tong Yu

AU - Breuer, Melvin A.

AU - Annavaram, Murali

AU - Gupta, Sandeep K.

AU - Lee, Kuen-Jong

PY - 2009/12/15

Y1 - 2009/12/15

N2 - To provide a new avenue for improving yield for nanoscale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.

AB - To provide a new avenue for improving yield for nanoscale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.

UR - http://www.scopus.com/inward/record.url?scp=76549124009&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=76549124009&partnerID=8YFLogxK

U2 - 10.1109/TEST.2009.5355594

DO - 10.1109/TEST.2009.5355594

M3 - Conference contribution

SN - 9781424448678

T3 - Proceedings - International Test Conference

BT - International Test Conference, ITC 2009 - Proceedings

ER -

Hsieh TY, Breuer MA, Annavaram M, Gupta SK, Lee K-J. Tolerance of performance degrading faults for effective yield improvement. In International Test Conference, ITC 2009 - Proceedings. 2009. 5355594. (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2009.5355594