Top-down methodology based low-dropout regulator design using Verilog-A

Chia Cheng Pao; Yan Chih Chen; Chien-Hung Tsai

doi:10.1109/ICSICT.2014.7021500

Top-down methodology based low-dropout regulator design using Verilog-A

Chia Cheng Pao, Yan Chih Chen, Chien-Hung Tsai

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.

Original language	English
Title of host publication	Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
Editors	Jia Zhou, Ting-Ao Tang
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932962
DOIs	https://doi.org/10.1109/ICSICT.2014.7021500
Publication status	Published - 2014 Jan 23
Event	2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 - Guilin, China Duration: 2014 Oct 28 → 2014 Oct 31

Publication series

Name	Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014

Other

Other	2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
Country/Territory	China
City	Guilin
Period	14-10-28 → 14-10-31

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Computer Science Applications

Access to Document

10.1109/ICSICT.2014.7021500

Cite this

Pao, C. C., Chen, Y. C., & Tsai, C.-H. (2014). Top-down methodology based low-dropout regulator design using Verilog-A. In J. Zhou, & T.-A. Tang (Eds.), Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 Article 7021500 (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT.2014.7021500

Pao, Chia Cheng ; Chen, Yan Chih ; Tsai, Chien-Hung. / Top-down methodology based low-dropout regulator design using Verilog-A. Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. editor / Jia Zhou ; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014).

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title = "Top-down methodology based low-dropout regulator design using Verilog-A",

abstract = "This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.",

author = "Pao, {Chia Cheng} and Chen, {Yan Chih} and Chien-Hung Tsai",

year = "2014",

month = jan,

day = "23",

doi = "10.1109/ICSICT.2014.7021500",

language = "English",

series = "Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Jia Zhou and Ting-Ao Tang",

booktitle = "Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014",

address = "United States",

note = "2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 ; Conference date: 28-10-2014 Through 31-10-2014",

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Pao, CC, Chen, YC & Tsai, C-H 2014, Top-down methodology based low-dropout regulator design using Verilog-A. in J Zhou & T-A Tang (eds), Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014., 7021500, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, Institute of Electrical and Electronics Engineers Inc., 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, Guilin, China, 14-10-28. https://doi.org/10.1109/ICSICT.2014.7021500

Top-down methodology based low-dropout regulator design using Verilog-A. / Pao, Chia Cheng; Chen, Yan Chih; Tsai, Chien-Hung.
Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. ed. / Jia Zhou; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2014. 7021500 (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Top-down methodology based low-dropout regulator design using Verilog-A

AU - Pao, Chia Cheng

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AU - Tsai, Chien-Hung

PY - 2014/1/23

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N2 - This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.

AB - This paper presents a top-down design methodology, which adopts the analog modeling methodology and mixed-level simulation strategy together, for low-dropout regulators (LDO) with low ESR output capacitor. The proposed methodology helps designers to verify the sub-block specifications before designing transistors and reduce design iterations, benefiting cost optimization. All the macro-models are developed in Verilog-A under a Cadence Spectre platform and used in the design flow. A design case implemented in TSMC 0.35μm CMOS technology is presented that shows how this methodology supports system design. Simulation and measurement results expose high similarity, making it a useful and efficient way for LDO design.

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BT - Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014

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Pao CC, Chen YC, Tsai CH. Top-down methodology based low-dropout regulator design using Verilog-A. In Zhou J, Tang TA, editors, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 7021500. (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014). doi: 10.1109/ICSICT.2014.7021500

Top-down methodology based low-dropout regulator design using Verilog-A

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