Topological cell compaction via transistor rotation

In this paper we propose a new algorithm for layout compaction by modifying the topology of a given layout. Different from most compaction algorithms which move the components of a layout, our algorithm compacts a layout by changing the orientations of transistors. A set of operations including moving, adding, deleting, shrinking, extending, etc., can work on the wires to rebuild and compact the layout after rotating a transistor. The simulated annealing technique is adopted in our algorithm to find a near optimal solution.