Toward automatic synthesis of SOC test platforms

Employing a test platform in an SOC design to execute test procedures can greatly simplify many SOC test problems. It, however, would require tremendous human efforts if the test platform would be generated manually. In this paper, we describe a design automation system, called DASTEP (Design Automation System for SOC TEst Platform), that is aimed to help users build a test platform and incorporate their IP designs into the platform. DASTEP provides an interactive mode to allow users to modify individual IP cores into 1149.1- or 1500-compatible ones and integrate them into the test platform. For a hierarchical core, DASTEP can synthesize a hierarchical test control architecture such that each core in the hierarchy can be efficiently tested in a 1149.1-compatible manner. All of the test procedures using this test platform are carried out on the chip through the cooperation of an embedded processor that usually exists in an SOC design and a dedicated test-access-mechanism (TAM) controller that can be automatically generated. Appropriate simulation environment that allows the simulation of the entire test flow is also created in conjunction with the generation of the test hardware/software, hence the verification of both core design and test plan can be readily carried out. A friendly graphic user interface tool is also developed that can greatly simplify the generation and simulation of the test platform.