Training-based forming process for RRAM yield improvement

Hsiu Chuan Shih, Ching Yi Chen, Cheng Wen Wu, Chih He Lin, Shyh Shyuan Sheu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)


Over the past decade, the resistive memory device known as RRAM has been studied extensively in many ways, and many of its problems have been identified, discussed, and some solved. It is time to move from material, process, and device to circuit design and yield, in order to commercialize RRAM. However, as we move from resistive device to memory circuit, new problems do appear, partly because the operating conditions of resistive devices on real RRAM circuit differ from those in an experimental environment for single devices. In this paper, an over forming problem has been identified from our analysis, and we propose a solution based on training sequence. As a result, by solving the over forming problem, RRAM yield can be improved significantly. RRAM; forming process; training sequence; yield improvement; non-volatile memory; memory testing

Original languageEnglish
Title of host publicationProceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011
Number of pages6
Publication statusPublished - 2011 Jul 1
Event2011 29th IEEE VLSI Test Symposium, VTS 2011 - Dana Point, CA, United States
Duration: 2011 May 12011 May 5

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2011 29th IEEE VLSI Test Symposium, VTS 2011
Country/TerritoryUnited States
CityDana Point, CA

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering


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