Transaction-level error susceptibility for bus-based system-on-chip: From single-bit to multi-bit

Shi Qun Zheng, Ing-Chao Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

System-on-Chip architectures have traditionally relied upon bus-based interconnect for their communication needs. The increasing bus frequencies and load on the bus calls for focus on reliability issues in such bus-based systems. As technology advances and transistor geometry shrinks, both single-bit and multi-bit error rate increase significantly. The scant research on mulit-bit errors calls for more attention about them. In this paper, we compare the consequences of a single-bit and multi-bit error and provide a detail analysis of a multi-bit error on the bus system during the course of different transactions. Such transaction based analysis helps us to develop an effective prediction methodology to predict the effect of a multi-bit error on any application running on a bus based architecture. We demonstrate that our transaction based prediction scheme works with an average accuracy of 88% over all the benchmarks when compared with the actual simulation results.

Original languageEnglish
Title of host publicationICS 2010 - International Computer Symposium
Pages670-675
Number of pages6
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International Computer Symposium, ICS 2010 - Tainan, Taiwan
Duration: 2010 Dec 162010 Dec 18

Publication series

NameICS 2010 - International Computer Symposium

Other

Other2010 International Computer Symposium, ICS 2010
CountryTaiwan
CityTainan
Period10-12-1610-12-18

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All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Zheng, S. Q., & Lin, I-C. (2010). Transaction-level error susceptibility for bus-based system-on-chip: From single-bit to multi-bit. In ICS 2010 - International Computer Symposium (pp. 670-675). [5685428] (ICS 2010 - International Computer Symposium). https://doi.org/10.1109/COMPSYM.2010.5685428