Transaction level error susceptibility model for bus based SoC architectures

Ing-Chao Lin, S. Srinivasan, N. Vijaykrishnan, N. Dhanwada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls for focus on reliability issues in such bus based systems. In this paper, we provide a detailed analysis of different kinds of errors and the susceptibility of such systems to such errors on various components that the bus comprises of. With elaborate experiments we determine the effect of a single bit error on the bus system during the course of different transactions. The work demonstrates the fact that only a few signals in a bus system are really critical and need to be guarded. Such transaction based analysis helps us to develop an effective prediction methodology to predict the effect of a single bit error on any application running on a bus based architecture. We demonstrate that our transaction based prediction scheme works with an average accuracy of 92% over all the benchmarks when compared with the actual simulation results.

Original languageEnglish
Title of host publicationProceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
Pages775-780
Number of pages6
DOIs
Publication statusPublished - 2006 Dec 1
Event7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
Duration: 2006 Mar 272006 Mar 29

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other7th International Symposium on Quality Electronic Design, ISQED 2006
CountryUnited States
CitySan Jose, CA
Period06-03-2706-03-29

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Lin, I-C., Srinivasan, S., Vijaykrishnan, N., & Dhanwada, N. (2006). Transaction level error susceptibility model for bus based SoC architectures. In Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006 (pp. 775-780). [1613230] (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2006.138