Transaction level modeling and design space exploration for SOC test architectures

Chin Yao Chang, Chih Yuan Hsiao, Kuen-Jong Lee, Alan P. Su

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan-or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external controlis carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the designspace of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.

Original languageEnglish
Title of host publicationProceedings of the 18th Asian Test Symposium, ATS 2009
Pages200-205
Number of pages6
DOIs
Publication statusPublished - 2009 Dec 1
Event18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
Duration: 2009 Nov 232009 Nov 26

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other18th Asian Test Symposium, ATS 2009
CountryTaiwan
CityTaichung
Period09-11-2309-11-26

Fingerprint

System buses
Built-in self test
Testing
Program processors
Data storage equipment
Intellectual property core

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chang, C. Y., Hsiao, C. Y., Lee, K-J., & Su, A. P. (2009). Transaction level modeling and design space exploration for SOC test architectures. In Proceedings of the 18th Asian Test Symposium, ATS 2009 (pp. 200-205). [5359358] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2009.33
Chang, Chin Yao ; Hsiao, Chih Yuan ; Lee, Kuen-Jong ; Su, Alan P. / Transaction level modeling and design space exploration for SOC test architectures. Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. pp. 200-205 (Proceedings of the Asian Test Symposium).
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Chang, CY, Hsiao, CY, Lee, K-J & Su, AP 2009, Transaction level modeling and design space exploration for SOC test architectures. in Proceedings of the 18th Asian Test Symposium, ATS 2009., 5359358, Proceedings of the Asian Test Symposium, pp. 200-205, 18th Asian Test Symposium, ATS 2009, Taichung, Taiwan, 09-11-23. https://doi.org/10.1109/ATS.2009.33

Transaction level modeling and design space exploration for SOC test architectures. / Chang, Chin Yao; Hsiao, Chih Yuan; Lee, Kuen-Jong; Su, Alan P.

Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. p. 200-205 5359358 (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chang CY, Hsiao CY, Lee K-J, Su AP. Transaction level modeling and design space exploration for SOC test architectures. In Proceedings of the 18th Asian Test Symposium, ATS 2009. 2009. p. 200-205. 5359358. (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2009.33