Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Nagu Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing Chao Lin

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)

Abstract

Transaction-Level models have emerged as an efficient way of modeling systems-on-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transaction-based power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.

Original languageEnglish
Pages (from-to)105-125
Number of pages21
JournalDesign Automation for Embedded Systems
Volume10
Issue number2-3
DOIs
Publication statusPublished - 2005 Sep

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

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