TY - GEN
T1 - Transformation of multiple fault models to a unified model for ATPG efficiency enhancement
AU - Wu, Cheng Hung
AU - Lee, Kuen Jong
PY - 2016/7/2
Y1 - 2016/7/2
N2 - This paper presents a systematic approach to transform various fault models to a unified model such that all faults of interest can be handled in one ATPG run. The fault models that can be transformed include, but are not limited to, stuck-At faults, various types of bridging faults, and cell-internal faults. The unified model is the aggressor-victim type of bridging fault model. Two transformation methods, namely fault-based and pattern-based transformations, are developed for cell-external and cell-internal faults, respectively. With the proposed approach, one can use an ATPG tool for bridging faults to deal with the test generation problems of multiple fault models simultaneously. Hence the total test generation time can be reduced and highly compact test sets can be obtained. Experimental results show that on average 54.94% (16.45%) and 47.22% (17.51%) test pattern volume reductions are achieved compared to the method that deals with the three fault models separately without (with) fault dropping for ISCAS'89 andIWLS'05 circuits, respectively.
AB - This paper presents a systematic approach to transform various fault models to a unified model such that all faults of interest can be handled in one ATPG run. The fault models that can be transformed include, but are not limited to, stuck-At faults, various types of bridging faults, and cell-internal faults. The unified model is the aggressor-victim type of bridging fault model. Two transformation methods, namely fault-based and pattern-based transformations, are developed for cell-external and cell-internal faults, respectively. With the proposed approach, one can use an ATPG tool for bridging faults to deal with the test generation problems of multiple fault models simultaneously. Hence the total test generation time can be reduced and highly compact test sets can be obtained. Experimental results show that on average 54.94% (16.45%) and 47.22% (17.51%) test pattern volume reductions are achieved compared to the method that deals with the three fault models separately without (with) fault dropping for ISCAS'89 andIWLS'05 circuits, respectively.
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U2 - 10.1109/TEST.2016.7805866
DO - 10.1109/TEST.2016.7805866
M3 - Conference contribution
T3 - Proceedings - International Test Conference
BT - Proceedings - 2016 IEEE International Test Conference, ITC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 47th IEEE International Test Conference, ITC 2016
Y2 - 15 November 2016 through 17 November 2016
ER -